Power efficiency enhancement analysis of an inverse class D power amplifier for NB-IoT applications

Abstract

The power amplifiers (PAs) are generally the most power-consuming building blocks in Radio Frequency (RF) transceivers. This paper presents a high efficiency fully integrated inverse class D power amplifier for the narrowband Internet of Things (NB-IoT) applications. In this design, the PA's power added efficiency (PAE) is improved by inserting two auxiliary PMOS transistors into the conventional topology of class D−1 PA, and the chip area is reduced by proper selection of the RF choke. An on-chip balun is designed to combine the output power of the two transistors, while its primary equivalent inductor resonates with a capacitor at the fundamental frequency. Based on simulation results, the proposed PA achieves 16.5 dBm output power with a peak power added efficiency (PAE) of 51.3%, while operating from a 1-V supply. Moreover, the proposed PA demonstrates the power gain of 21.6 dB and drain efficiency of 57% at the frequency band of 1.85–1.91 GHz. By using 180 nm TSMC technology, the proposed PA occupies a total chip area of 1.19 mm2 (0.85 mm × 1.4 mm), including pads