An Intelligent ATPG Technique Based On Meta-Heuristic Algorithms

Abstract

This paper explores the advancements in Very Large Scale Integrated (VLSI) circuit testing, with a focus on enhancing fault detection methodologies that are crucial for smart systems. In the realm of smart systems—such as IoT devices, autonomous vehicles, and smart appliances—accurate fault detection is vital due to the complexity of integrated circuits used in these technologies. Traditional fault detection tests usually categorize circuits as either functional or faulty, lacking the ability to pinpoint specific faults, which limits their effectiveness in intricate applications. The growing complexity of circuit designs and the variations in manufacturing processes highlight the pressing need for precise fault localization during both pre-production and testing phases. Our analysis of the ISCAS'89 benchmark circuits demonstrates the significant efficacy of the Particle Swarm Optimization (PSO)-optimized FAN algorithm. This approach has resulted in notable improvements in fault coverage, ranging from 0.01% to 2.32%, alongside an overall enhancement in fault detection efficiency. These results indicate not only an increase in the number of detected faults but also a reduction in the number of required test vectors, ultimately improving testing efficiency for large-scale production scenarios, crucial for the reliability of smart systems.